1. Field of the Invention
The invention relates to a recording head of an ink jet system for recording onto a recording medium by discharging ink and to a recording apparatus using such a recording head.
2. Related Background Art
FIG. 13 is a diagram showing a circuit construction of a recording head mounted in a recording apparatus of a conventional ink jet system. An electrothermal converting element (heater) of such a kind of recording head and its drive circuit can be formed on a same substrate by using a semiconductor processing technique as shown in, for example, U.S. Pat. No. 6,290,334 (corresponding to Japanese Patent Application Laid-Open No. H05-185594).
As shown in FIG. 13, reference numeral 101 denotes electrothermal converting elements (heaters) as recording elements each for generating heat to discharge ink; 102 n-type power transistors as switching elements each for supplying a desired current to the heater 101; and 106 a shift register for supplying a current to each heater 101 and temporarily storing image data to decide whether or not the ink is discharged from a nozzle of the recording head. A transfer clock signal input terminal (CLK) and an image data input terminal (DATA) for serially inputting image-data for turning on/off the heaters 101 are provided for the shift register 106. Reference numeral 105 denotes latch circuits each for recording and holding the image data for the heater 101 every heater. A latch signal input terminal (LT) for inputting an output of the shift register 106 and inputting a latch signal to control latch timing is provided for the latch circuit 105. Reference numeral 104 denotes AND circuits. Each AND circuit 104 inputs an output of the latch circuit 105 and a heating signal (HE) to decide timing for supplying the current to the heater 101. An output of the AND circuit 104 is inputted to a gate of the n-type power transistor 102 through a voltage conversion circuit 103.
The n-type power transistor 102 comprises, for example, a field effect transistor such as nMOS transistor, n-type DMOS (diffusion MOS), or the like.
A circuit construction of the voltage conversion circuit 103 will be described. Reference numeral 208 denotes a first inverter circuit for inverting the image data from the AND circuit 104; 207 a second inverter circuit for further inverting a signal outputted from the first inverter circuit 208; 202 a pMOS transistor; and 203 an nMOS transistor. A first CMOS inverter circuit is constructed by the pMOS transistor 202 and the nMOS transistor 203. Reference numeral 201 denotes a first pMOS transistor for buffering. In order to enable the first CMOS inverter circuit to be driven at a voltage which is equal to or less than 5V as an output voltage of the AND circuit (a power voltage of the logic unit is generally equal to or less than 5V), the first pMOS transistor 201 for buffering divides a voltage supplied from an internal power line VHTM which is outputted from a voltage generating circuit 107. Reference numeral 205 denotes a pMOS transistor and 206 indicates an nMOS transistor. A second CMOS inverter circuit is constructed by the pMOS transistor 205 and the nMOS transistor 206. Reference numeral 204 denotes a second pMOS transistor for buffering. A gate of the second pMOS transistor 204 for buffering is connected to a connecting portion of the pMOS transistor 202 and the nMOS transistor 203 as an output portion of the first CMOS inverter circuit forming a pair with the second CMOS inverter circuit. Similarly, a gate of the first pMOS transistor 201 for buffering is also connected to a connecting portion of the pMOS transistor 205 and the nMOS transistor 206 as an output portion of the second CMOS inverter circuit forming a pair with the first CMOS inverter circuit and this connecting portion also functions as an output portion of the voltage conversion circuit.
It is desirable to set the output voltage VHTM of the voltage generating circuit 107 to as high a value as possible without exceeding a breakdown withstanding voltage of the CMOS inverter and a gate withstanding voltage of the MOS. If possible, the output voltage VHTM can be made common to a power line VH of the heater. However, a driving voltage of the general heater is often set as a relatively high voltage of 20V or more and the breakdown withstanding voltage of the CMOS inverter is often formed by a process of up to about 15V. Since the gate withstanding voltage of the MOS depends on a gate oxide film, it is also necessary to set the breakdown withstanding voltage to a value lower enough than an insulative withstanding voltage the gate oxide film. Therefore, it is difficult to make the driving voltage of the heater to coincide with the optimum voltage of the voltage conversion circuit. If the power line of the voltage conversion circuit is separately provided, it results in an increase in costs of the whole system.
In the conventional technique, therefore, the voltage generating circuit 107 is realized by a circuit construction as shown in FIG. 14.
In the circuit construction as shown in FIG. 14, an arbitrary voltage is formed from the power line VH of the heater by a voltage dividing ratio of resistors R0 and R1 and inputted to a source-follower circuit constructed by an nMOS transistor T1 as a buffer and a resistor R2. A source of the nMOS transistor T1 is used as an output terminal of the voltage generating circuit 107.
FIG. 15 is a timing chart for various signals to drive the drive circuit of the recording head shown in FIG. 13. The drive circuit of the recording head shown in FIG. 13 will be described with reference to FIG. 15 and the like.
A transfer clock signal (CLK) and an image data signal (DATA) are inputted to the shift register 106. The shift register 106 operates synchronously with a leading edge of the transfer clock signal CLK. Since the number of bits of the image data (DATA) stored in the shift register 106 is equal to the number of heaters 101 and the number of power transistors 102, pulses of transfer clock signals (CLK) as many as the number of heaters 101 are inputted and the image data (DATA) is transferred to the shift register 106. Thereafter, by supplying the latch signal (LT), the image data (DATA) corresponding to each heater 101 is held in the latch circuit 105. After that, the AND of an output of the latch circuit 105 and the heat signal (HE) is calculated (AND process). A current is supplied from the power line VH to the power transistor 102 and the heater 101 for the time corresponding to the output of the AND circuit and flows in the GNDH line. At this time, the heater 101 generates heat necessary to discharge the ink, so that the ink according to the image data is discharged from the nozzle of the recording head.
The circuit construction described above has been disclosed in Japanese Patent Application Laid-Open-No. H11-129479 as a Japanese Patent Laid-Open Publication.
However, according to the above prior art, since the output voltage VHTM of the voltage generating circuit 107 is determined by the voltage dividing ratio of the resistors R0 and R1, the voltage generating circuit 107 depends largely on a fluctuation in power line to which the heater 101 is connected. There is, consequently, such a problem that when the output voltage VHTM fluctuates, a resistance (ON resistance) at the time of conduction of the power transistor changes and a desired discharging energy cannot be obtained.
When it is necessary to adjust the discharging energy, generally, the heat energy generated by the heater 101 is adjusted by changing the power voltage of the power line VH. However, if the power voltage of the power line VH is changed, since the output voltage VHTM fluctuates, such adjustment cannot be made after the recording head is manufactured. Therefore, to adjust the discharging energy, it is necessary to design the drive circuit of the recording head again and newly manufacture it. Consequently, such a problem that developing time of the recording head becomes long and its developing costs increase occurs.
The invention is made in consideration of the above problems and it is an object of the invention to provide a recording head having a voltage generating circuit which does not depend on a fluctuation in heater driving voltage (first power voltage) and a recording apparatus using such a recording head.